1. Field of the Invention
The present invention relates to interconnect structures and a method of making them. More particularly, the present invention relates to a dual damascene interconnect structure having a thin non-porous low-k dielectric layer and a liner material between the metal via and line conductors and the dielectric layers. The interconnect structures are suitable for use in high-speed microprocessors, application specific integrated circuits (ASIC's) and other high speed integrated circuits (IC's).
2. Description of the Prior Art
Many low-k dielectric plus Cu interconnect structures of the dual damascene type are known. For an example of the dual damascene process wherein SiLK™ can be used as a low-k dielectric material, reference is made to U.S. Pat. No. 6,383,920, which is assigned to the same assignee as the present invention, the contents of which are incorporated herein by reference in their entirety as if fully set forth. In order to achieve the necessary reduction in the RC delay in future generations of integrated circuits, porous materials must be used as the dielectric. In addition, due to the 5-20 nanometer pore sizes of porous organic materials, a buried etch stop layer is necessary to give smooth metal line bottoms. However, in conventional integration of an organic dielectric where a cap layer is deposited above the prior level of metallization before depositing the insulator materials, challenges to the dual damascene integration of porous dielectrics arise from the inability to achieve etch selectivity of low-k etch stops to both the organic dielectric and the inorganic (typically SiN or SiCN) cap layer.
An illustration of dual damascene integration with an embedded etch stop and a cap layer can be found in to U.S. Pat. No. 6,448,176 B1, FIG. 1. The lack of etch selectivity between the embedded etch stop and cap does not cause poor line profiles with a dense dielectric because the lines stop on the etch stop in the dielectric etch, then go just through the etch stop and stop on the via level dielectric during the cap open RIE step. When using porous dielectrics, if the etch stop is removed at the bottom of the line a rough line bottom created from the porosity in the via level dielectric will result. Also, the line and via sidewalls can have a surface roughness equivalent to the size of the pores in the dielectric leading to defects in the liner. In addition, the choices of materials for the etch stop and cap layers necessary to achieve a low k effective, efficient raw process time and mechanical integrity of the stack are limited.